Top-down Physical Design of Soft Embedded FPGA Fabrics

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Abstract

Embedded FPGA (eFPGA) fabrics are finding increasing use in modern System-on-Chip designs as their programmability can be leveraged not only to accelerate a variety of workloads but also to enable upgradability, feature addition, and security. With technology scaling, designing hard eFPGA fabrics using full-custom layout techniques requires extensive design time/effort with poor process portability and is not compatible with typical SoC design schedules. On the other hand, soft eFPGA fabrics described in RTL and designed using standard-cells can significantly speed up the eFPGA design cycle and provide effortless process portability. Design methodologies for implementing soft FPGA fabrics presented in the literature typically employ a bottom-up approach wherein individual tiles are synthesized in isolation and later stitched together to generate the large FPGA fabric. However, using a bottom-up methodology to ensure fabric-level performance targets is challenging due to the lack of a global timing view across multiple tiles spanning the FPGA fabric. While previous works address this problem with a combination of and manual buffering and floorplanning, these additional steps introduce significant deviations from standard push-button ASIC flows. In this paper, a top-down methodology is proposed, which eliminates the need for floorplanning and manual buffering by providing a global timing view of the FPGA fabric to the electronic design automation (EDA) tools. Experimental results on a 28nm industrial CMOS process demonstrate that the top-down methodology results in fabrics with up to 20% improvement in performance without the need for any manual buffering or floorplanning. A proof of concept 16x16 tile FPGA fabricated on an industrial 16nm CMOS FinFET process occupies a core area of 1.74mm2 and can operate up to 630MHz.