A Generic Synthesisable Test Bench
The work
| Authors | Matthew Naylor; Simon Moore |
|---|---|
| Editors | |
| Type | inproceedings |
| Year | 2015 |
| Citekey | naylor2015generic |
Where it appeared
| Published in | 2015 ACM/IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE) |
|---|---|
| Pages | 128--137 |
Identifiers
| DOI | 10.1109/memcod.2015.7340479 |
|---|
Access
| Landing page | https://www.repository.cam.ac.uk/handle/1810/253007 |
|---|
Related
| Distinct from | camilleri1988simulation |
|---|---|
| Distinct from | joannou2024randomized |
From bibtex.
Abstract
Writing test benches is one of the most frequently-performed tasks in the hardware development process. The ability to reuse common test bench features is therefore key to productivity. In this paper, we present a generic test bench, parameterised by a specification of correctness, which can be used to test any design. Our test bench provides several important features, including automatic test-sequence generation and shrinking of counter-examples, and is fully synthesisable, allowing rigorous testing on FPGA as well as in simulation. The approach is easy to use, cheap to implement, and encourages the formal specification of hardware components through the reward of automatic testing and simple failure cases.
A copy is held
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How it got here
| How it got here | agent via bibtex |
|---|---|
| Added | 2026-09-18 08:11 UTC |
| Approved by | a person 2026-09-18 10:09 UTC |
Filed under
Cite it as
@inproceedings{naylor2015generic,
title = {A Generic Synthesisable Test Bench},
author = {Matthew Naylor and Simon Moore},
year = {2015},
booktitle = {2015 ACM/IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE)},
pages = {128--137},
doi = {10.1109/memcod.2015.7340479},
}
This record lives at https://refs.drheap.org/naylor2015generic/ and will keep doing so.