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RF2: A 1GHz FIR Filter with Distributed Resonant Clock Generator
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Abstract
In this paper we present the design and experimental validation of RF2, a 1 GHz, two-phase resonant-clocked FIR filter test-chip with a distributed resonant clock generator and an on-chip inductor. RF2 is fabricated in a 0.13μm CMOS process and dissipates 124mW at resonance, with clock power accounting for only 16% of overall power. Implemented using a fully ASIC design flow, RF2 achieves 84% clock-power efficiency overCV2f, the highest for any fully-integrated resonant-clocked chip. Resonating at 1.01GHz, RF2 reports the highest operating frequency for a resonant-clocked datapath to date.
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Cite it as
@misc{sathe2007rf2,
title = {RF2: A 1GHz FIR Filter with Distributed Resonant Clock Generator},
author = {Visvesh Sathe and Jerry C. Kao and Marlos C. Papaefthymiou},
year = {2007},
journal = {IEEE Symposium on VLSI Circuits (VLSI-Circuits)},
pages = {44--45},
doi = {10.1109/vlsic.2007.4342759},
}