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Resonant-Clock Design for a Power-Efficient, High-Volume x86-64 Microprocessor

The work

AuthorsVisvesh Sathe; Srikanth Arekapudi; Alexander T. Ishii; Charles Ouyang; Marios C. Papaefthymiou; Samuel Naffziger
Editors
Typearticle
Year2013
Also known assathe2012resonantclock
Citekeysathe2013resonantclock

Where it appeared

Published inIEEE Journal of Solid-State Circuits
PublisherInstitute of Electrical and Electronics Engineers
Volume48
Issue1
Pages140--149

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Abstract

AMD's 32-nm x86-64 core code-named “Piledriver” features a resonant global clock distribution to reduce clock distribution power while maintaining a low clock skew. To support a wide range of operating frequencies expected of the core, the global clock system operates in two modes: a resonant-clock (rclk) mode for energy-efficient operation over a desired frequency range and a conventional, direct-drive mode (cclk) to support low-frequency operation. This dual-mode feature was implemented with minimal area impact to achieve both reduced average power dissipation and improved power-constrained performance. In Piledriver, resonant clocking achieves a peak 25% global clock power reduction at 75°C, which translates to a 4.5% reduction in average application core power.

How it got here

How it got hereagent via openalex
Added2026-10-27 17:40 UTC
Not denied bya person 2026-10-29 17:12 UTC

Cite it as

@article{sathe2013resonantclock,
  title        = {Resonant-Clock Design for a Power-Efficient, High-Volume x86-64 Microprocessor},
  author       = {Visvesh Sathe and Srikanth Arekapudi and Alexander T. Ishii and Charles Ouyang and Marios C. Papaefthymiou and Samuel Naffziger},
  year         = {2013},
  journal      = {IEEE Journal of Solid-State Circuits},
  publisher    = {Institute of Electrical and Electronics Engineers},
  volume       = {48},
  number       = {1},
  pages        = {140--149},
  doi          = {10.1109/jssc.2012.2218068},
}

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