VERIFY: evaluation of reliability using VHDL-models with embedded fault descriptions
The work
| Authors | Volkmar Sieh; Oliver Tschäche; Frank J. Balbach |
|---|---|
| Editors | |
| Type | misc |
| Year | 1997 |
| Also known as | sieh2002verify |
| Citekey | sieh1997verify |
Where it appeared
| Pages | 32--36 |
|---|
Identifiers
| DOI | 10.1109/ftcs.1997.614074 |
|---|---|
| OpenAlex | W2135577965 |
Access
| Landing page | https://doi.org/10.1109/ftcs.1997.614074 |
|---|
From OpenAlex, which stores abstracts as an index of words and their positions: what is shown is rebuilt from that, and reads fluently whether or not it is what the author wrote.
Abstract
A new technique for reliability evaluation of digital systems will be presented by demonstrating the functionality and usage of the simulation based fault injector VERIFY (VHDL-based Evaluation of Reliability by Injecting Faults efficientlY). This software tool introduces a new way for describing the behavior of hardware components in case of faults by extending the VHDL language with fault injection signals together with their rate of occurrence. The accuracy of the results is obtained by using the same VHDL-models which have been developed during conventional phases of hardware design. For demonstrating the capabilities of VERIFY, a VHDL-model of a simple 32-bit processor (DP32) will be used as an example to illustrate the several steps of reliability evaluation.
How it got here
| How it got here | agent via openalex |
|---|---|
| Added | 2026-10-26 06:10 UTC |
| Not denied by | a person 2026-10-29 17:12 UTC |
Cite it as
@misc{sieh1997verify,
title = {VERIFY: evaluation of reliability using VHDL-models with embedded fault descriptions},
author = {Volkmar Sieh and Oliver Tschäche and Frank J. Balbach},
year = {1997},
pages = {32--36},
doi = {10.1109/ftcs.1997.614074},
}
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