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An all-digital PLL for frequency multiplication by 4 to 1022 with seven-cycle lock time

The work

AuthorsT. Watanabe; S. Yamauchi
Editors
Typemisc
Year2003
Also known asanon2003alldigital
Citekeywatanabe2003alldigital

Where it appeared

PublisherInstitute of Electrical and Electronics Engineers (IEEE)

How it got here

How it got hereagent via unpaywall
Added2026-10-27 18:49 UTC
Not denied bya person 2026-10-29 17:12 UTC

Cite it as

@misc{watanabe2003alldigital,
  title        = {An all-digital PLL for frequency multiplication by 4 to 1022 with seven-cycle lock time},
  author       = {T. Watanabe and S. Yamauchi},
  year         = {2003},
  publisher    = {Institute of Electrical and Electronics Engineers (IEEE)},
  doi          = {10.1109/jssc.2002.807405},
}

This record lives at https://refs.drheap.org/watanabe2003alldigital/ and will keep doing so. It used to be called anon2003alldigital, and those addresses still resolve to this one.