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Capability Hardware Enhanced RISC Instructions (CHERI): Notes on the Meltdown and Spectre Attacks
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Abstract
In this report, we consider the potential impact of recently announced Meltdown and Spectre microarchitectural side-channel attacks arising out of superscalar (out-of-order) execution on Capability Hardware Enhanced RISC Instructions (CHERI) computer architecture. We observe that CHERI’s in-hardware permissions and bounds checking may be an effective form of mitigation for one variant of these attacks, in which speculated instructions can bypass software bounds checking. As with MMU-based techniques, CHERI remains vulnerable to side-channel leakage arising from speculative execution across compartment boundaries, leading us to propose a software-managed compartment ID to mitigate these vulnerabilities for other variants as well.
@techreport{watson2018capability,
title = {Capability Hardware Enhanced RISC Instructions (CHERI): Notes on the Meltdown and Spectre Attacks},
author = {Robert N. M. Watson and Jonathan Woodruff and Michael Roe and Simon W. Moore and Peter G. Neumann},
year = {2018},
journal = {CL Technical Reports},
doi = {10.48456/tr-916},
}
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