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Yosys: a free verilog synthesis suite

The work

AuthorsC. Wolf; J. Glaser; J. Kepler
Editors
Typeinproceedings
Year2013
Citekeywolf2013yosys

Where it appeared

Published inProceedings of the 21st Austrian Workshop on Microelectronics (Austrochip)

How it got here

How it got hereagent via bibtex
Added2026-10-24 03:11 UTC
Not denied bya person 2026-10-29 17:12 UTC

Cite it as

@inproceedings{wolf2013yosys,
  title        = {Yosys: a free verilog synthesis suite},
  author       = {C. Wolf and J. Glaser and J. Kepler},
  year         = {2013},
  booktitle    = {Proceedings of the 21st Austrian Workshop on Microelectronics (Austrochip)},
}

This record lives at https://refs.drheap.org/wolf2013yosys/ and will keep doing so.