Two Papers on a Symbolic Analyzer for MOS Circuits
Where it appeared
| Publisher | Carnegie Mellon University, Computer Science Department |
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| Number in series | CMU-CS-87-106 |
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| School | Carnegie Mellon University, Computer Science Department |
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From bibtex.
Abstract
This report contains two papers describing a set of algorithms to extract the logical behavior of a digital metal-oxide semiconductor (MOS) from its transistor representation. Switch-level network analysis, applied symbolically, performs the extraction. The analyzer captures all aspects of switch-level networks including bidirectional transistors, stored charge, different signal strengths, and indeterminate (X) logic values. The output is a set of Boolean formulas, where the behavior of each network node is represented by a pair of formulas. In the worst case, the analysis of an n node network can yield a set of formulas containing a total of O(n^3) Boolean operations. However, all but a limited set of dense, pass transistor networks give formulas with O(n) total operations. The analyzer can serve as the basis of efficient programs for a variety of logic design tasks, including: logic simulation (on both conventional and special purpose computers), fault simulation, test generation, and symbolic verification. These papers have been accepted for publication in IEEE Transactions on Computer-Aided Design of Integrated Circuits.