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Peter G. Neumann

Peter G. Neumann, SRI: the CHERI project's other long-standing name, on the rigorous ISA specification and the three Cambridge hardware-security records of 2023-24. Four records.

Safe Speculation for CHERI

Franz A. Fuchs and others (2024) · 2024 IEEE 42nd International Conference on Computer Design (ICCD)

Randomized Testing of RISC-V CPUs Using Direct Instruction Injection

Alexandre Joannou and others (2024) · IEEE Design and Test

Architectural Contracts for Safe Speculation

Franz A. Fuchs and others (2023) · 2023 IEEE 41st International Conference on Computer Design (ICCD)

Cornucopia: Temporal Safety for CHERI Heaps

Nathaniel Wesley Filardo and others (2020) · Proceedings - IEEE Symposium on Security and Privacy/Proceedings of the ... IEEE Symposium on Security and Privacy · IEEE Computer Society

Rigorous Engineering for Hardware Security: Formal Modelling and Proof in the CHERI Design and Implementation Process

Kyndylan Nienhuis and others (2020) · 2020 IEEE Symposium on Security and Privacy (SP)

Capability Hardware Enhanced RISC Instructions: CHERI Instruction-Set Architecture (Version 8)

Robert N. M. Watson and others (2020) · CL Technical Reports

CheriABI: Enforcing valid pointer provenance and minimizing pointer privilege in the POSIX C run-time environment

Brooks Davis and others (2019) · ASPLOS 2019: Proceedings of the 24th International Conference on Architectural Support for Programming Languages and Operating Systems

Capability Hardware Enhanced RISC Instructions: CHERI Instruction-Set Architecture (Version 7)

Robert N. M. Watson and others (2019) · CL Technical Reports

CHERI Concentrate: Practical Compressed Capabilities

Jonathan Woodruff and others (2019) · Institute of Electrical and Electronics Engineers (IEEE)

Fundamental Trustworthiness Principles in CHERI

Peter G. Neumann (2018) · The MIT Press

Risks to the Public

Peter G. Neumann (2018) · Association for Computing Machinery (ACM)

Capability Hardware Enhanced RISC Instructions (CHERI): Notes on the Meltdown and Spectre Attacks

Robert N. M. Watson and others (2018) · CL Technical Reports

Capability Hardware Enhanced RISC Instructions: CHERI Instruction-Set Architecture (Version 6)

Robert N. M. Watson and others (2017) · Computer Laboratory, University of Cambridge

Capability Hardware Enhanced RISC Instructions: CHERI Instruction-Set Architecture (Version 5)

Robert N. M. Watson and others (2016) · CL Technical Reports

Fast Protection-Domain Crossing in the CHERI Capability-System Architecture

Robert N. M. Watson and others (2016) · IEEE Micro · Institute of Electrical and Electronics Engineers

CHERI: A Hybrid Capability-System Architecture for Scalable Software Compartmentalization

Robert N. M. Watson and others (2015) · Proceedings - IEEE Symposium on Security and Privacy/Proceedings of the ... IEEE Symposium on Security and Privacy · IEEE Computer Society

The CHERI capability model: Revisiting RISC in an age of risk

Jonathan Woodruff and others (2014) · IEEE

PSOS revisited

Peter G. Neumann and others (2003) · Annual Computer Security Applications Conference

The foundations of a provably secure operating system (PSOS)

Richard J. Feiertag and others (1979) · IEEE