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Fast Protection-Domain Crossing in the CHERI Capability-System Architecture
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Abstract
Capability Hardware Enhanced RISC Instructions (CHERI) supplement the conventional memory management unit (MMU) with instruction-set architecture (ISA) extensions that implement a capability system model in the address space. CHERI can also underpin a hardware-software object-capability model for scalable application compartmentalization that can mitigate broader classes of attack. This article describes ISA additions to CHERI that support fast protection-domain switching, not only in terms of low cycle count, but also efficient memory sharing with mutual distrust. The authors propose ISA support for sealed capabilities, hardware-assisted checking during protection-domain switching, a lightweight capability flow-control model, and fast register clearing, while retaining the flexibility of a software-defined protection-domain transition model. They validate this approach through a full-system experimental design, including ISA extensions, a field-programmable gate array prototype (implemented in Bluespec SystemVerilog), and a software stack including an OS (based on FreeBSD), compiler (based on LLVM), software compartmentalization model, and open-source applications.
@article{watson2016fast,
title = {Fast Protection-Domain Crossing in the CHERI Capability-System Architecture},
author = {Robert N. M. Watson and Robert M. Norton and Jonathan Woodruff and Simon W. Moore and Peter G. Neumann and Jonathan Anderson and David Chisnall and Brooks Davis and Ben Laurie and Michael Roe and Nirav Dave and Khilan Gudka and Alexandre Joannou and A. Theodore Markettos and Ed Maste and Steven J. Murdoch and Colin Rothwell and Stacey Son and Munraj Vadera},
year = {2016},
journal = {IEEE Micro},
publisher = {Institute of Electrical and Electronics Engineers},
volume = {36},
number = {5},
pages = {38--49},
doi = {10.1109/mm.2016.84},
}