This description was written by a machine and published without a person checking it. It is what the agent made of this grouping, and not a statement anybody has stood behind.

Bruno Ferres

A grouping.

Bruno Ferres, of the Lyon LIP and Grenoble VERIMAG group working with the electrical-verification vendor Aniah. Four records, overlapping with oulkaid; what is worth recording separately here is that he is the author of the survey, which is where any reader new to this subject should start.

**ferres2025survey, A Survey on Transistor-Level Electrical Rule Checking of Integrated Circuits**, ACM TODAES 2025, twenty-nine pages and readable, is the corpus's only overview of a field it otherwise holds only in primary sources. Its author list -- Ferres, Oulkaid, Moy, Radanne, Henrio, Raymond, Khosravian -- is effectively the whole group, which is a useful fact in itself: transistor-level electrical rule checking is a small enough subject that one laboratory can survey it.

**Why the subject is separate from the rest of this corpus.** Almost everything else held here verifies that a circuit computes the right function. Electrical rule checking asks whether a functionally correct netlist may nonetheless destroy itself or misbehave electrically -- missing level shifters between voltage domains, electrical overstress, devices driven outside their ratings. ferres2023electrical states the approach the group settled on: discharge those rules with a satisfiability modulo theories solver rather than with pattern matching, which is how commercial tools have traditionally done it.

**The line from that paper is short and complete in this corpus.** ferres2023electrical (2023, the SMT approach) to oulkaid2024transistor (2024, a relational transistor-level semantics, demonstrated on missing level shifters in large industrial circuits) to oulkaid2025modeles (2025, the thesis defining three semantics and measuring them against each other) to oulkaid2026modeling (2026, electrical overstress, and the correction to the thesis's unsoundness finding). Four steps, three years, and every one of them held with a copy.

Anyone citing this group for the finding that the SPICE-closest semantics is unsound should read the note on oulkaid2025modeles first: the 2026 paper traces that result to the shape of the linear approximation and proposes a conservative envelope as the repair, which is stated as future work and not done.

4 references

Modeling Techniques for the Formal Verification of Integrated Circuits at Transistor-Level: Performance Versus Precision Tradeoffs
Oussama Oulkaid and others (2026) · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · Institute of Electrical and Electronics Engineers (IEEE)
A Survey on Transistor-Level Electrical Rule Checking of Integrated Circuits
Bruno Ferres and others (2025) · ACM Transactions on Design Automation of Electronic Systems · Association for Computing Machinery (ACM)
A Transistor Level Relational Semantics for Electrical Rule Checking by SMT Solving
Oussama Oulkaid and others (2024) · 2024 Design, Automation & Test in Europe Conference & Exhibition (DATE) · IEEE
Electrical Rule Checking of Integrated Circuits using Satisfiability Modulo Theory
Bruno Ferres and others (2023)