Electrical Rule Checking of Integrated Circuits using Satisfiability Modulo Theory

The work

AuthorsBruno Ferres; Oussama Oulkaid; Ludovic Henrio; M. Khosravian G.; Matthieu Moy; Gabriel Radanne; Pascal Raymond
Editors
Typemisc
Year2023
Citekeyferres2023electrical

Where it appeared

Pages1--2

Related

Distinct frombiere1999symbolic
Distinct frombryant1982mossim
Distinct frombryant1991methodology
Distinct fromdhingra1987formal
Distinct fromelshehaby2023susceptibility
Distinct fromferres2025survey
Distinct fromleeser1988reasoning
Distinct frommateescu2020modeling
Distinct fromoulkaid2024transistor
Distinct fromoulkaid2025modeles
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From OpenAlex, which stores abstracts as an index of words and their positions: what is shown is rebuilt from that, and reads fluently whether or not it is what the author wrote.

Abstract

We consider the verification of electrical properties of circuits to identify potential violations of electrical design rules, also called Electrical Rule Checking (ERC). We present a general approach based on Satisfiability Modulo Theory (SMT) to verify that these errors cannot occur in a given circuit. We claim that our approach is scalable and more precise than existing analyses, like voltage propagation. We applied these techniques to a specific type of errors, the missing level shifters. On an industrial case-study, our technique is able to flag 31 % of the warnings raised by the voltage propagation analysis as being false alarms.

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Added2026-09-16 01:43 UTC
Approved bya person 2026-09-16 09:16 UTC

Cite it as

@misc{ferres2023electrical,
  title        = {Electrical Rule Checking of Integrated Circuits using Satisfiability Modulo Theory},
  author       = {Bruno Ferres and Oussama Oulkaid and Ludovic Henrio and M. Khosravian G. and Matthieu Moy and Gabriel Radanne and Pascal Raymond},
  year         = {2023},
  pages        = {1--2},
  doi          = {10.23919/date56975.2023.10137147},
}

This record lives at https://refs.drheap.org/ferres2023electrical/ and will keep doing so.