Formal validation of an integrated circuit design style
The work
| Authors | Inderpreet-Singh Dhingra |
|---|---|
| Editors | |
| Type | techreport |
| Year | 1987 |
| Citekey | dhingra1987formal |
Where it appeared
| Publisher | University of Cambridge Computer Laboratory |
|---|---|
| Number in series | UCAM-CL-TR-115 |
| School | University of Cambridge Computer Laboratory |
Identifiers
| DOI | 10.48456/tr-115 |
|---|---|
| report_number | UCAM-CL-TR-115 |
| ISSN | 1476-2986 |
Access
| Landing page | https://www.cl.cam.ac.uk/techreports/UCAM-CL-TR-115.html |
|---|
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From bibtex.
Abstract
In dynamic circuit design many rules must be followed which govern the correctness of the design. In this paper a dynamic CMOS design style using a two phase non-overlapping clock with its intricate design rules is presented together with formal means of showing that a circuit follows these rules.
A copy is held
pdf, 1.1 MB. Not published — it may be under copyright. The facts and links here are.
How it got here
| How it got here | agent via bibtex |
|---|---|
| Added | 2026-09-16 00:03 UTC |
| Approved by | a person 2026-09-23 14:11 UTC |
Filed under
Cite it as
@techreport{dhingra1987formal,
title = {Formal validation of an integrated circuit design style},
author = {Inderpreet-Singh Dhingra},
year = {1987},
publisher = {University of Cambridge Computer Laboratory},
school = {University of Cambridge Computer Laboratory},
issn = {1476-2986},
doi = {10.48456/tr-115},
}
This record lives at https://refs.drheap.org/dhingra1987formal/ and will keep doing so.