Hierarchical Verification of Asynchronous Circuits Using Temporal Logic
The work
| Authors | Bud Mishra; Edmund M. Clarke |
|---|---|
| Editors | |
| Type | article |
| Year | 1985 |
| Citekey | mishra1985hierarchical |
Where it appeared
| Published in | Theoretical Computer Science |
|---|---|
| Publisher | North-Holland |
| Volume | 38 |
| Pages | 269--291 |
Identifiers
| DOI | 10.1016/0304-3975(85)90223-3 |
|---|
Access
| Landing page | https://www.cs.cmu.edu/~emc/papers/Papers%20In%20Refereed%20Journals/Hierarchical%20Verification%20of%20Asynchronous%20Circuits%20Using%20Temporal%20Logic.pdf |
|---|
Related
| Distinct from | bozga2002verification |
|---|---|
| Distinct from | browne1986automatic |
| Distinct from | burlyaev2015design |
| Distinct from | clarke1981design |
| Distinct from | tollec2024formal |
From bibtex.
Abstract
Establishing the correctness of complicated asynchronous circuit is in general quite difficult because of the high degree of nondeterminism that is inherent in such devices. Nevertheless, it is also very important in view of the cost involved in design and testing of circuits. We show how to give specifications for circuits in a branching time temporal logic and how to mechanically verify them using a simple and efficient model checker. We also show how to tackle a large and complex circuit by verifying it hierarchically.
A copy is held
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How it got here
| How it got here | agent via bibtex |
|---|---|
| Added | 2026-09-17 07:55 UTC |
| Approved by | a person 2026-09-18 14:22 UTC |
Filed under
Cite it as
@article{mishra1985hierarchical,
title = {Hierarchical Verification of Asynchronous Circuits Using Temporal Logic},
author = {Bud Mishra and Edmund M. Clarke},
year = {1985},
journal = {Theoretical Computer Science},
publisher = {North-Holland},
volume = {38},
pages = {269--291},
doi = {10.1016/0304-3975(85)90223-3},
}
This record lives at https://refs.drheap.org/mishra1985hierarchical/ and will keep doing so.