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19.1 Computationally Enabled Total Energy Minimization Under Performance Requirements for a Voltage-Regulated 0.38-to-0.58V Microprocessor in 65nm CMOS
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Abstract
Integrated circuits for ultra-low-power applications strive to minimize total system energy, while satisfying performance requirements. The supply voltage (\(V_{dd}\)) can be set to a Minimum Energy Point (MEP) [1, 2], where leakage and dynamic energy are suitably balanced. However, controlling operating frequency (\(f_{c/k}\)), while concurrently tracking a MEP sensitive to PVT and switching activity is not possible. Meanwhile, the traditional approach of locking to the minimum required frequency (\(f_{targ}\)), and adiusting \(V_{dd}\)to maintain timing slack precludes the possibility of minimum-energy computing. Therefore, there exists a need for a minimum-energy computing architecture that meets performance requirements.
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Cite it as
@misc{urrahman2019191,
title = {19.1 Computationally Enabled Total Energy Minimization Under Performance Requirements for a Voltage-Regulated 0.38-to-0.58V Microprocessor in 65nm CMOS},
author = {Fahim ur Rahman and Venkata Rajesh Pamula and Akshat Boora and Xun Sun and Visvesh Sathe},
year = {2019},
journal = {Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference},
publisher = {Institute of Electrical and Electronics Engineers},
pages = {312--314},
doi = {10.1109/isscc.2019.8662486},
}