Advanced Clocking and Power Management Techniques for Microprocessors

From bibtex.

Abstract

Ensuring high performance and low-power is the goal for almost all system-on-chips (SoCs). With the recent slow-down in technology scaling, innovations in circuits and systems are playing a significant role to improve the power-performance metric. This thesis proposed different techniques in clocking and power management of microprocessors to enable high-performance and energy-efficient operation while ensuring robustness across process, voltage and temperature variation. We proposed new circuit techniques, computational control or innovations in system-level that demonstrated substantial improvement in several key areas. Switching energy is clock distribution constitutes a significant portion of power budget of SoCs. To reduce the clocking power in a system, resonant clocking technique was proposed. But resonant-clocking has limitations in frequency scaling. We propose quasi-resonant clocking (QRC), a new technique to achieve frequency scalability in resonant clocked system. QRC made resonant clocking viable for voltage-frequency scalable systems. In modern microprocessors, latency in clock generation and frequency switching affects the processor start-up time and causes delay in resolving cache coherence request in multi-core systems. A fast-locking PLL can improve the latency and performance of multi-core systems. We analyzed the reason for longer lock-time in PLLs and came up with computational-locking, a new approach to achieve lock in PLL that improves the lock-time substantially. Measurement result from 65nm test-chips demonstrate significant improvement in lock-time. To further improve the power-performance metric, we analyzed the advantages and imitations of existing clock power architectures and implemented unified clock and power architecture (UniCaP). One of the limitations of traditional architecture is the system needs significantly large voltage margin against supply droop and temperature variation. In this thesis we show how UniCaP drastically reduces the voltage margin while ensuring performance regulation. We demonstrated UniCaP in a switched-capacitor based sub-threshold system, fabricated 65nm CMOS process. Measurement result demonstrated significant reduction of voltage-margin, resulting in significant energy savings. We minimized the energy dissipation of the ultra-low power UniCaP system further by implementing a self-energy minimization feature. The system operates in minimum energy-per-cycle point while satisfying the performance requirements. We analyzed the energetics of switched-capacitor and derived the expression for energy-per-cycle (EPC). Then we constructed a system that will estimate the EPC at different voltages and through comparison will approach the minimum energy-per-cycle point. We implemented the system in 65nm test-chip and measurement result demonstrated MEP-operation across temperature and load variation with less than 5mV of error.