Extraction of Gate Level Models from Transistor Circuits by Four-Valued Symbolic Analysis
The work
| Authors | Randal E. Bryant |
|---|---|
| Editors | |
| Type | inproceedings |
| Year | 1991 |
| Citekey | bryant1991extraction |
Where it appeared
| Published in | International Conference on Computer-Aided Design (ICCAD '91) |
|---|---|
| Pages | 350--353 |
Access
| Landing page | https://www.cs.cmu.edu/~bryant/pubdir/iccad91.pdf |
|---|
Related
| Distinct from | bryant1987boolean |
|---|---|
| Distinct from | bryant1987cosmos |
| Distinct from | dhingra1988formalising |
| Distinct from | joyce1987hardware |
| Distinct from | leeser1988reasoning |
| Distinct from | slobodova2011flexible |
From bibtex.
Abstract
The program TRANALYZE generates a gate-level representation of an MOS transistor circuit. The resulting model contains only four-valued unit and zero delay logic primitives, suitable for evaluation by conventional gate-level simulators and hardware simulation accelerators. TRANALYZE has the same generality and accuracy as switch-level simulation, generating models for a wide range of technologies and design styles, while expressing the detailed effects of bidirectional transistors, stored charge, and multiple signal strengths. It produces models with size comparable to ones generated by hand.
A copy is held
pdf, 63.6 kB. Not published — it may be under copyright. The facts and links here are.
How it got here
| How it got here | agent via bibtex |
|---|---|
| Added | 2026-09-16 21:33 UTC |
| Approved by | a person 2026-09-17 17:09 UTC |
Filed under
Cite it as
@inproceedings{bryant1991extraction,
title = {Extraction of Gate Level Models from Transistor Circuits by Four-Valued Symbolic Analysis},
author = {Randal E. Bryant},
year = {1991},
booktitle = {International Conference on Computer-Aided Design (ICCAD '91)},
pages = {350--353},
}
This record lives at https://refs.drheap.org/bryant1991extraction/ and will keep doing so.