From the transistor to the end of scaling

A subject the papers are about. The loosest grouping, and the one to reach for last.

The transistor, the integrated circuit, and the scaling rules that made each shrink pay for itself. Collects the founding device and process documents, Moore and Dennard, the papers arguing over where scaling stops, and the physical floors the shrink runs into. Most of its members are held as citations only, so the arguments are readable here and much of the primary record they argue over is not.

The set holds two floors, and they are different in kind. Landauer's is thermodynamic and quantitative -- erasing a bit costs at least kT ln 2, described in 1961 and measured fifty-one years later by Berut and others. Marino's is logical and qualitative: no physical implementation of a non-trivial digital circuit can deterministically avoid, resolve or detect metastability, so no bistable can be relied on to have settled. One says what computing costs; the other says what it cannot promise.

It also holds the modelling layer between the device and the circuit -- Arora's compact MOSFET models, which is what simulation actually computes with, and at the far end ab-initio quantum transport, which is what it costs when the compact abstraction stops holding. Those are the set's own statement of its limits, and the bridge to the-switch-or-the-curve, which asks the same question from the correctness side rather than the simulation side.

The post-CMOS candidates are here too -- tunnelling FETs, carbon nanotube FETs, ternary logic, cryogenic operation. Read them against gargini2017brief and the Moore retrospectives, which supply the industry's own record of how often a successor device has been announced.